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| SI5600 P R E L I M I N A R Y DA TA S H E E T SiPHY TM OC-192/STM-64 SONET/SDH TRANSCEIVER Features Complete low power, high speed, SONET/SDH transceiver with integrated limiting amp, CDR, CMU, and MUX/DEMUX ! Data Rates Supported: OC-192/ ! SONET Compliant Loop Timed STM-64, 10GbE, and 10.7 Gbps FEC Operation ! Low Power Operation 1.2 W (typ) ! Programmable Slicing Level and Sample Phase Adjustment ! DSPLLTM Based Clock Multiplier Unit w/ Selectable Loop Filter Bandwidths ! SFI-4 Compliant Low Speed Interface ! Integrated Limiting Amplifier ! Single Supply 1.8 V Operation ! Loss-of-Signal (LOS) Alarm ! 15 x 15 mm BGA Package ! Diagnostic and Line Loopbacks SI5600 Bottom View Applications ! Ordering Information: ! Sonet/SDH Transmission Systems Optical Transceiver Modules ! Sonet/SDH Test Equipment See page 25. Description The SI5600 is a complete low-power transceiver for high-speed serial communication systems operating between 9.9 Gbps and 10.7 Gbps. The receive path consists of a fully integrated limiting amplifier, clock and data recovery unit (CDR), and 1:16 deserializer. The transmit path combines a low jitter clock multiplier unit (CMU) with a 16:1 serializer. The CMU uses Silicon Laboratories' DSPLLTM technology to provide superior jitter performance while reducing design complexity by eliminating external loop filter components. To simplify BER optimization in long haul applications, programmable slicing, and sample phase adjustment are supported. The SI5600 operates from a single 1.8 V supply over the industrial temperature range (-40C to 85C). Functional Block Diagram P H AS E AD J S L IC E L V L LO S LOSLVL 1:16 DEMUX R X D IN REFSEL Loopback Control REFCLK LP TM R E F R ATE TXLO L BW SEL TX C LK DS B L TX C LKO U T TX S Q LC H TXDO UT RESET 2 FIFO 16:1 MUX 2 RESET C o n tro l LLBK DLBK 2 T X C L K 1 6 IN 2 L im itin g AMP RXLOL RXSQ LCH RXM SBSEL 32 LTR CDR R X D O U T [1 5 :0 ] 2 / 2 RXCLK1 RXCLK2 R X C L K 2 D IV RXCLK2DSBL D S P L L TM TX C M U / 2 2 32 TX C LK 16O U T T X C L K 1 6 IN T X D IN [1 5 :0 ] F IF O R S T F IF O E R R TXM SBSEL Preliminary Rev. 0.31 8/01 Copyright (c) 2001 by Silicon Laboratories SI5600-DS031 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. SI5600 2 Preliminary Rev. 0.31 SI5600 TABLE O F CONTENTS Section Page 4 12 12 12 12 13 13 13 13 14 14 15 15 15 16 17 19 25 26 28 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Data Recovery (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSPLLTM Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Timed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SI5600 Pinout: 195-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: SI5600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preliminary Rev. 0.31 3 SI5600 Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature LVTTL Output Supply Voltage SI5600 Supply Voltage Symbol TA VDD33 VDD Test Condition Min* -40 1.71 1.71 Typ 25 -- 1.8 Max* 85 3.47 1.89 Unit C V V *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25C unless otherwise stated. V SIGNAL + Differential VICM, VOCM SIGNAL - I/Os VIS Single Ended Voltage (SIGNAL +) - (SIGNAL -) Differential Voltage Swing VID,VOD (VID = 2VIS) Differential Peak-to-Peak Voltage t Figure 1. Differential Voltage Measurement (RXDIN, RXDOUT, RXCLK1, RXCLK2, TXDIN, TXDOUT, TXCLKOUT, TXCLK16OUT, TXCLK16IN) tsu TXDOUT, TXDIN tCP thd tCH TXCLKOUT, TXCLK16IN RXDOUT RXCLK1 tcq1 tcq2 Figure 2. Data to Clock Delay 4 Preliminary Rev. 0.31 SI5600 80% 20% tF tR All Differential IOs Figure 3. Rise/Fall Time Measurement Table 2. DC Characteristics (VDD = 1.8 V 5%, TA = -40C to 85C) Parameter Symbol Test Condition Min Typ Max Unit Supply Current Power Dissipation Voltage Reference (VREF) Common Mode Input Voltage (RXDIN) Differential Input Voltage Swing (RXDIN) Common Mode Output Voltage (TXDOUT, TXCLKOUT) Differential Output Voltage Swing (TXDOUT, TXCLKOUT), Differential pk-pk LVPECL Input Voltage HIGH (REFCLK) LVPECL Input Voltage LOW (REFCLK) LVPECL Input Voltage Swing, Differential pk-pk (REFCLK) LVPECL Internally Generated Input Bias (REFCLK) LVDS Input High Voltage (TXDIN, TXCLK16IN) LVDS Input Low Voltage (TXDIN, TXCLK16IN) LVDS Input Voltage, Single Ended pk-pk (TXDIN, TXCLK16IN) LVDS Output High Voltage (RXDOUT, RXCLK1, RXCLK2, TXCLK16OUT) LVDS Output Low Voltage (RXDOUT, RXCLK1, RXCLK2, TXCLK16OUT) LVDS Output Voltage, Differential pk-pk (RXDOUT, RXCLK1, RXCLK2, TXCLK16OUT) IDD PD VREF VICM VID VOCM VOD VIH VIL VID VIB VIH VIL VISE VOH1 100 Load Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line, Figure 1 Figure 1 See Figure 1 See Figure 1 VREF driving 10 k load -- -- 1.21 TBD 20 .8 800 1.975 1.32 250 1.6 -- 0.0 100 TBD 611 1.2 1.25 0.1 -- 0.9 1000 2.3 1.6 -- 1.95 -- -- -- -- TBD TBD 1.29 TBD 1.0 1.0 1200 2.59 1.99 2400 2.3 2.4 -- 600 1.475 mA W V V mV (pk-pk) V mV (pk-pk) V V mV (pk-pk) V V V mV (pk-pk) mV VOL1 0.925 -- TBD V VOSE 500 -- 800 mV (pk-pk) Preliminary Rev. 0.31 5 SI5600 Table 2. DC Characteristics (Continued) (VDD = 1.8 V 5%, TA = -40C to 85C) Parameter Symbol Test Condition Min Typ Max Unit LVDS Common Mode Voltage (RXDOUT, RXCLK1, RXCLK2, TXCLK16OUT) Input Impedance (TXDIN, TXCLK16IN, REFCLK, RXDIN) Output Short to GND (RXDOUT, RXCLK1, RXCLK2, TXCLK16OUT, TXDOUT, TXCLKOUT) Output Short to VDD (RXDOUT, RXCLK1, RXCLK2, TXCLK16OUT, TXDOUT, TXCLKOUT) LVTTL Input Voltage Low (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET, TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, TXMSBSEL, DLBK, LLBK, LPTM) LVTTL Input Voltage High (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET, TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, TXMSBSEL, DLBK, LLBK, LPTM) LVTTL Input Low Current (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET, TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, TXMSBSEL, DLBK, LLBK, LPTM) LVTTL Input High Current (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET, TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, TXMSBSEL, DLBK, LLBK, LPTM) LVTTL Input Impedance (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET, TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, TXMSBSEL, DLBK, LLBK, LPTM) LVTTL Output Voltage Low (LOS, RXLOL, FIFOERR, TXLOL) LVTTL Output Voltage High (LOS, RXLOL, FIFOERR, TXLOL) VCM 1.125 -- 1.275 V RIN ISC(-) Each input to common mode 42 -- 50 25 58 TBD mA ISC(+) TBD -100 -- A VIL2 VDD33 = 3.3 V VDD33 = 1.8 V -- -- -- -- 0.8 0.7 V VIH2 VDD33 = 3.3 V VDD33 = 1.8 V 2.0 1.7 -- -- V IIL -- -- 10 A IIH -- -- 10 A RIN 10 -- -- k VOL2 VOH2 VDD33 = 1.8 V VDD33 = 3.3 V VDD33 = 1.8 V VDD33 = 3.3 V -- -- 1.4 2.4 -- -- -- -- 0.4 0.4 -- -- V V 6 Preliminary Rev. 0.31 SI5600 Table 3. AC Characteristics (RXDIN, RXDOUT, RXCLK1, RXCLK2) (VDD = 1.8 V 5%, TA = -40C to 85C) Parameter Symbol Test Condition Min Typ Max Unit Output Clock Frequency (RXCLK1) Duty Cycle (RXCLK1, RXCLK2) Output Rise and Fall Times (RXCLK1, RXCLK2,RXDOUT) Data Invalid Prior to RXCLK1 Data Invalid After RXCLK1 Input Return Loss (RXIN) Slicing Adjust Dynamic Range Slicing Level Offset (referred to RXDIN) 1 fclkout tch/tcp, Figure 2 tR,tF tcq1 tcq2 Figure 3 Figure 2 Figure 2 400 kHz-10.0 GHz 10.0 GHz-16.0 GHz SLICELVL = 200-800 mV SLICELVL = 200-800 mV VSLICE 2 -- 45 -- -- -- 18.7 TBD -20 -500 -5 -45 10 -500 -5 622 -- 50 -- -- -- -- -- -- -- -- -- -- -- 667 55 -- 200 200 -- -- 20 500 5 45 o MHz % ps ps ps dB dB mV V Slicing Level Accuracy Sampling Phase Adjustment LOS Threshold Dynamic Range LOS Threshold Offset3 (referred to RXDIN) LOS Threshold Accuracy % mV pk-pk V PHASEADJ = 200-800 mV LOSLVL = 200-800 mV LOSLVL = 200-800 mV VLOS 50 500 5 % Note: 1. Slice level (referred to RXDIN) is calculated as follows: VSLICE = (SLICE_LVL - 0.4 " VREF)/15. 2. Sample Phase Offset is calculated as follows: PHASE OFFSET = 45 (PHASEADJ - 0.4 " VREF)/0.3 3. LOS Threshold voltage (referred to RXDIN) is calculated as follows: VLOS = 30 mV + (LOS_LVL - 0.4 " VREF)/15. Preliminary Rev. 0.31 7 SI5600 Table 4. AC Characteristics (TXCLK16OUT, TXCLK16IN, TXCLKOUT, TXDIN, TXDOUT) (VDD = 1.8 V 5%, TA = -40C to 85C) Parameter Symbol Test Condition Min Typ Max Unit TXCLKOUT Frequency TXCLKOUT Duty Cycle Output Rise Time (TXCLKOUT, TXDOUT) Output Fall Time (TXCLKOUT, TXDOUT) TXCLKOUT Setup to TXDOUT TXCLKOUT Hold From TXDOUT Output Return Loss TXCLK16OUT Frequency TXCLK16OUT Duty Cycle TXCLK16OUT Rise & Fall Times TXDIN Setup to TXCLK16IN TXDIN Hold from TXCLK16IN TXCLK16IN Frequency TXCLK16IN Duty Cycle TXCLK16IN Rise & Fall Times fclkout tch/tcp, Figure 2 tR tF tsu thd Figure 3 Figure 3 Figure 2 Figure 2 400 kHz-10 GHz 10 GHz-16 GHz fCLKIN tch/tcp, Figure 2 tR,tF tDSIN tDHIN fCLKIN tch/tcp, Figure 2 tR,tF -- 45 -- -- 25 25 TBD TBD -- 40 100 -- -- -- 40 100 9.95 -- 25 25 -- -- -- -- 622 -- -- -- -- 622 -- -- 10.7 55 -- -- -- -- -- -- 667 60 300 300 300 667 60 300 GHz % ps ps ps ps dB dB MHz % ps ps ps MHz % ps 8 Preliminary Rev. 0.31 SI5600 Table 5. AC Characteristics (Receiver PLL) (VDD = 1.8 V 5%, TA = -40C to 85C) Parameter Symbol Test Condition Min Typ Max Unit Jitter Tolerance JTOL(PP) f = 2.4 kHz f = 24 kHz f = 400 kHz f = 4 MHz 15 1.5 1.5 0.15 -- 30 3.0 3.0 0.3 -- 622 155 50 -- 600 -- -- -- -- 20 667 167 60 100 1000 UIpp UIpp UIpp UIpp s Acquisition Time TAQ REFRATE = 1 REFRATE = 0 Input Reference Clock Frequency RCFREQ -- -- 40 -100 TBD MHz MHz % ppm ppm Reference Clock Duty Cycle Reference Clock Frequency Tolerance Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) Frequency Difference at which Receive PLL goes into Lock (REFCLK compared to the divided down VCO clock) RCDUTY RCTOL LOL LOCK TBD 300 TBD ppm Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998. Preliminary Rev. 0.31 9 SI5600 Table 6. AC Characteristics (Transmitter Clock Multiplier Characteristics) (VDD = 1.8 V 5%, TA = -40C to 85C) Parameter Symbol Test Condition Min Typ Max Unit Jitter Generation--Deterministic Jitter Generation--Random Jitter Transfer Bandwidth JDET(PP) JGEN(RMS) JBW PRBS 23 -- -- 0.020 0.005 -- -- 0.05 15 622 155 -- -- TBD TBD 12 50 0.1 20 667 167 60 100 UIPP UIRMS kHz kHz dB mS MHz MHz % ppm BWSEL = 0 BWSEL = 1 -- -- -- Jitter Transfer Peaking Acquisition Time Input Reference Clock Frequency TAQ RCFREQ Valid REFCLK REFRATE = 1 REFRATE = 0 Input Reference Clock Duty Cycle Input Reference Clock Frequency Tolerance RCDUTY RCTOL -- -- -- 40 -100 Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998. Table 7. Absolute Maximum Ratings Parameter Symbol Value Unit DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any Output PIN Operating Junction Temperature Storage Temperature Range Package Temperature (soldering 10 seconds) ESD HBM Tolerance (100 pf, 1.5 k) VDD VDD33 VDIF -0.5 to TBD -0.5 to 3.6 -0.3 to (VDD+ 0.3) 50 V V V mA C C C TJCT TSTG -55 to 150 -55 to 150 275 TBD V Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 8. Thermal Characteristics Parameter Symbol JA Test Condition Value Unit C/W Thermal Resistance Junction to Ambient Still Air 38 10 Preliminary Rev. 0.31 SI5600 LVTTL Control Inputs TXMSBEL TXCLKDSBL RXMSBSEL TXSQLCH RXSQLCH RXCLK2DSBL RXCLK2DIV REFSEL REFRATE LPTM BWSEL DLBK LLBK LTR FIFOERR FIFORST TXLOL RXLOL RESET 0.033 F FIFO Over/Underflow Loss-of-Lock Indicator Loss-of-Signal Indicator 16 LOS RXDOUT High Speed Serial Input LVPECL Reference Clock LVDS Parallel Data 16 Input RXDIN LVDS Recovered Parallel Data LVDS Recovered Low Speed Clock SI5600 REFCLK RXCLK1 RXCLK2 0.033 F TXDIN TXDOUT 0.033 F High Speed Serial Data Output High Speed Clock Output Low Speed Clock Output Voltage Reference Output (1.25 V) LVDS Data Clock Input TXCLKOUT TXCLK16IN TXCLK16OUT PHASEADJ SLICELVL RXREXT TXREXT VREF GND 0.1 F 2200 pF 20 pF LOSLVL VDD Loss-of-Signal Data Slice Level Set Level Set Sampling Phase Level Set Figure 4. SI5600 Typical Application Circuit Preliminary Rev. 0.31 VDD 11 SI5600 Functional Description The SI5600 transceiver is a low power, fully integrated serializer/deserializer that provides significant margin to all SONET/SDH jitter specifications. The device operates from 9.9-10.7 Gbps making it suitable for OC192/STM-64, 10GbE, and OC-192/STM-64 applications that use 15/14 forward error correction (FEC) coding. The low speed receive/transmit interface uses LVDS I/ Os that are compliant to the Optical Interface Forum's SFI-4 standard. LOSLVL pin, and VREF is reference voltage output on the VREF pin. The LOS detection circuitry is disabled by tieing the LOSLVL input to the supply (VDD). This forces the LOS output high. Slicing Level Adjustment Receiver The receiver within the SI5600 includes a precision limiting amplifier, high jitter tolerance clock and data recovery unit (CDR), and 1:16 demultiplexer. In addition, programmable data slicing and sampling phase adjustment are provided to support bit-error-rate (BER) optimization for long haul applications. To support applications that require BER optimization, the limiting amplifier provides circuitry that supports adjustment of the 0/1 decision threshold (slicing level) over a range of 20 mV when referred to the internally biased RXDIN input. The slicing level is set by applying a voltage between 0.20 V and 0.80 V to the SLICELVL input. The voltage present on SLICELVL sets the slicing level as follows: ( V SLICE - 0.4xVREF ) V LEVEL = ---------------------------------------------------------15 Limiting Amplifier The SI5600 incorporates a high sensitivity limiting amplifier with sufficient gain to directly accept the output of transimpedance amplifiers. High sensitivity is achieved by using a digital calibration algorithm to cancel out amplifier offsets. This algorithm achieves superior offset cancellation by using statistical averaging to remove noise that may degrade more traditional calibration routines. The limiting amplifier provides sufficient gain to fully saturate with input signals that are less than 20 mV peak-to-peak differential. In addition, input signals that exceed 1 V peak-to-peak differential will not cause any performance degradation. Loss-of-Signal (LOS) Detection VLEVEL is the slicing level referred to the RXDIN input, VSLICE is the voltage applied to the SLICE_LVL pin, and VREF is reference voltage output on the VREF pin. The slicing level adjustment may be disabled by tieing the SLCLVL input to the supply (VDD). When slicing is disabled, the slicing offset is set to 0.0 V relative to internally biased input common mode voltage for RXDIN. Clock and Data Recovery (CDR) The SI5600 uses an integrated CDR to recover clock and data from a non-return to zero (NRZ) signal input on RXDIN. The recovered data clock is used to regenerate the incoming data by sampling the output of the limiting amplifier at the center of the NRZ bit period. The recovered clock and data is then deserialized by a 1:16 demultiplexer and output via a LVDS compatible low speed interface (RXDOUT[15:0], RXCLK1, and RXCLK2). Sample Phase Adjustment The limiting amplifier includes circuitry that generates a loss-of-signal (LOS) alarm when the input signal amplitude on RXDIN falls below an externally controlled threshold. The SI5600 can be configured to drive the LOS output low when the differential input amplitude drops below a threshold set between ~10 mV and 50 mV pk-pk differential. Approximately 3 dB of hysteresis prevents unnecessary switching on LOS. The LOS threshold is set by applying a voltage between 0.20 V and 0.80 V to the LOSLVL input. The voltage present on LOSLVL maps to an input signal threshold as follows: ( V LOSLVL - 0.4xVREF ) V LOS = -------------------------------------------------------------- + 30 mV 15 In applications where it is not desirable to recover data by sampling in the center of the data eye, the SI5600 supports adjustment of the CDR sampling phase across the NRZ data period. When sample phase adjustment is enabled, the sampling instant used for data recovery can be moved over a range of 45 relative to the center of the incoming NRZ bit period. Adjustment of the sampling phase is desirable when data eye distortions are introduced by the transmission medium. The sample phase is set by applying a voltage between 0.20 V and 0.80 V to the PHASEADJ input. The voltage present on PHASEADJ maps to sample phase offset as follows: VLOS is the differential pk-pk LOS threshold referred to the RXDIN input, VLOSLVL is the voltage applied to the 12 Preliminary Rev. 0.31 SI5600 45x ( V PHASE - 0.4xVREF ) Phase Offset = ------------------------------------------------------------------------0.30 Phase Offset is the sampling offset in degrees from the center of the data eye, VPHASE is the voltage applied to the PHASEADJ pin, and VREF is reference voltage output on the VREF pin. A positive phase offset will adjust the sampling point to lead the default sampling point in the center of the data eye, and a negative phase offset will adjust the sampling point to lag the default sampling point. Data recovery using a sampling phase offset is disabled by tieing the PHASEADJ input to the supply (VDD). This forces a phase offset of 0 to be used for data recovery. Lock Detect output bus RXDOUT[15:0]. The mapping of the receive bits to the output data word is controlled by the RXMSBSEL input. If RXMSBSEL is tied low, the first bit received is output on RXDOUT0 and the following bits are output in order on RXDOUT1 through RXDOUT15. If RXMSBSEL is tied high, the first bit received is output on RXDOUT15, and the following bits are output in order on RXDOUT14 through RXDOUT0. Auxiliary Clock Output To support the widest range of system timing configurations, a second clock output is provided on RXCLK2. This output can be configured to provide a clock that is a 1/16th or 1/64th submultiple of the high speed recovered clock. The divide factor used to generate RXCLK2 is controlled via the RXCLKDIV2 input as described in "Pin Descriptions: SI5600" on page 19. In applications which do not use RXCLK2, this output can be powered down by forcing the RSCLK2DSBL input high. The SI5600 provides lock-detect circuitry that indicates whether the PLL has achieved frequency lock with the incoming data. This circuit compares the frequency of a divided down version of the recovered clock with the frequency of the supplied reference clock (REFCLK). If the recovered clock frequency deviates from that of the reference clock by the amount specified in Table 5 on page 9, the PLL is declared out of lock, and the loss-oflock (RXLOL) pin is asserted. In this state, the PLL will try to reacquire lock with the incoming data stream. During reacquisition, the recovered clock frequency (RXCLK1 and RXCLK2) will drift over a 1000 ppm range relative to the supplied reference clock. The RXLOL output will remain asserted until the recovered clock frequency is within the REFCLK frequency by the amount specified in Table 5 on page 9. Lock-to-Reference Data Squelch During some system error conditions, such as LOS, it may be desirable to force the receive data output to 0 in order to avoid propagation of erroneous data into the downstream electronics. In these applications, the SI5600 provides a data squelching control input, RXSQLCH. When this input is active low, the data on RXDOUT will be forced to 0. Data squelch is disabled if the device is operating in diagnostic loopback mode (DLBK = 0). Transmitter The transmitter consists of a low jitter, clock multiplier unit (CMU) with a 16:1 serializer. The CMU uses a phase-locked loop (PLL) architecture based on Silicon Laboratories' proprietary DSPLLTM technology. This technology is used to generate ultra-low jitter clock and data outputs that provide significant margin to the SONET/SDH specifications. The DSPLL architecture also utilizes a digitally implemented loop filter that eliminates the need for external loop filter components. As a result, sensitive noise coupling nodes that typically cause degraded jitter performance in crowded PCB environments are removed. The DSPLLTM also reduces the complexity and performance requirements of reference clock distribution strategies for OC-192/STM-64 optical port cards. This is possible because the DSPLL provides selectable wideband and narrowband loop filter settings that allow the user to set the jitter attenuation characteristics of the CMU to accommodate reference clock sources that have a high jitter content. Unlike 13 In applications where it is desirable to maintain a stable output clock during an alarm condition like loss-ofsignal, the lock-to-reference input (LTR) can be used to force a stable output clock. When LTR is asserted, the CDR is prevented from acquiring the data signal and the CDR will lock the RXCLKOUT1 and RXCLKOUT2 outputs to the provided REFCLK. In typical applications, the LOS output would be tied to the LTR input to force a stable output clock. Deserialization The SI5600 uses a 1:16 demultiplexer to deserialize the high speed input. The deserialized data is output on a 16-bit parallel data bus RXDOUT[15:0] synchronous with the rising edge of RXCLK1. This clock output is derived by dividing down the recovered clock by a factor of 16. Serial Input to Parallel Output Relationship The SI5600 provides the capability to select the order in which the received serial data is mapped to the parallel Preliminary Rev. 0.31 SI5600 traditional analog PLL implementations, the loop filter bandwidth is controlled by a digital filter inside the DSPLL and can be changed without any modification to external components. shift register by an output clock, TXCLK16OUT, that is produced by dividing down the high speed transmit clock, TXCLKOUT, by a factor of 16. The TXCLK16OUT clock output is provided to support 16-bit word transfers between the SI5600 and upstream devices using a counter clocking scheme. The high-speed serial data stream is clocked out of the shift register using TXCLKOUT. Input FIFO DSPLLTM Clock Multiplier Unit The SI5600's clock multiplier unit (CMU) uses Silicon Laboratories' proprietary DSPLL technology to generate a low jitter, high frequency clock source capable of producing a high speed serial clock and data output with significant margin to the SONET/SDH specifications. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage controlled oscillator (VCO). Because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the DSPLL less susceptible to board-level noise sources. Therefore, SONET/SDH jitter compliance is easier to attain in the application. Programmable Loop Filter Bandwidth The SI5600 integrates a FIFO to decouple data transferred into the FIFO via TXCLK16IN from data transferred into the shift register via TXCLK16OUT. The FIFO is eight parallel words deep and accommodates any static phase delay that may be introduced between TXCLK16OUT and TXCLK16IN in counter clocking schemes. Furthermore, the FIFO will accommodate a phase drift or wander between TXCLK16IN and TXCLK16OUT of up to three parallel data words. The FIFO circuitry indicates an overflow or underflow condition by asserting FIFOERR high. This output can be used to recenter the FIFO read/write pointers by tieing it directly to the FIFORST input. The SI5600 will also recenter the read/write pointers after the device's power on reset, external reset via RESET, and each time the DSPLL transitions from an out of lock state to a locked state (TXLOL transitions from low to high). Parallel Input To Serial Output Relationship The digitally implemented loop filter allows for two bandwidth settings that provide either wideband or narrowband jitter transfer characteristics. The filter bandwidth is selected via the BWSEL control input. In traditional PLL implementations, changing the loop filter bandwidth would require changing the values of external loop filter components. In narrowband mode, a loop filter cutoff of 12 kHz is provided. This setting makes the SI5600 more tolerant to jitter on the reference clock source. As a result, distribution circuitry used to generate the physical layer reference clocks can be simplified without compromising jitter margin to the SONET/SDH specification. In wideband mode, the loop filter provides a cutoff of 50 kHz. This setting is desirable in applications where the reference clock is provided by a low jitter source like the Si5364 Clock Synchronization IC or Si5320 Precision Clock Multiplier/Jitter Attenuator IC. This allows the DSPLL to more closely track the precision reference source, resulting in the best possible jitter performance. The SI5600 provides the capability to select the order in which data on the parallel input bus is transmitted serially. Data on this bus can be transmitted MSB first or LSB first depending on the setting of TXMSBSEL. If TXMSBSEL is tied low, TXDIN0 is transmitted first followed in order by TXDIN1 through TXDIN15. If TXMSBSEL is tied high, TXDIN15 is transmitted first followed in order by TXDIN14 through TXDIN0. This feature simplifies board routing when ICs are mounted on both sides of the PCB. Transmit Data Squelch To prevent the transmission of corrupted data into the network, the SI5600 provides a control pin that can be used to force TXDOUT to 0. By driving TXSQLCH low, the high speed serial output, TXDOUT will be forced to 0. Transmit data squelching is disabled when the device is in line loopback mode (LLBK = 0). Clock Disable Serialization The SI5600 includes serialization circuitry that combines a FIFO with a parallel to serial shift register. Low speed data on the parallel input bus, TXDIN[15:0], is latched into the FIFO on the rising edge of TXCLK16IN. The data in the FIFO is clocked into the The SI5600 provides a clock disable pin, TXCLKDSBL, that is used to disable the high-speed serial data clock output, TXCLKOUT. When the TXCLKDSBL pin is asserted, the positive and negative terminals of CLKOUT are tied to 1.5 V through 50 on-chip resistors. This feature is used to reduce power 14 Preliminary Rev. 0.31 SI5600 consumption in applications that do not use the high speed transmit data clock. reference clock submultiples of the data rate. The SI5600 supports operation with two selectable reference clock sources. The first configuration uses an externally provided reference clock that is input via REFCLK. The second configuration uses the parallel data clock, TXCLK16IN, as the reference clock source. When using TXCLK16IN as the reference source, the narrowband loop filter setting in the CMU may be preferable to remove jitter that may be present on the data clock. The selection of reference clock source is controlled via the REFSEL input. The CMU in the SI5600's transmit section multiplies up the provided reference to the serial transmit data rate. When the CMU has achieved lock with the selected reference, the TXLOL output will be driven high.The CDR in the receive section of the SI5600 uses a reference clock to center the PLL frequency so that it is close enough to the data frequency to achieve lock with the incoming data. When the CDR has locked to the data, RXLOL is driven high. Loop Timed Operation The SI5600 may be configured to provide SONET/SDH compliant loop timed operation. When LPTM is asserted high, the transmit clock and data timing is derived from the recovered clock output by the CDR. This is achieved by dividing down the recovered clock and using it as a reference source for the transmit CMU. This will produce a transmit clock and data that are locked to the timing recovered from the received data path. In this mode, a narrow band loop filter setting is recommended. Diagnostic Loopback The SI5600 supports diagnostic loopback which establishes a loopback path from the serializer output to the deserializer input. This provides a mechanism for looping back data input via the low speed transmit interface TXDIN to the low speed receive data interface RXDOUT. This mode is enabled by forcing DLBK low. Reset The SI5600 is reset by holding the RESET pin low for at least 1 s. When RESET is asserted low, the input FIFO pointers reset and the digital control circuitry initializes. When RESET transitions high to start normal operation, the CMU will be calibrated. Line Loopback The SI5600 supports line loopback which establishes a loopback path from the high speed receive input to the high speed transmit output. This provides a mechanism for looping back the high-speed clock and data recovered from RXDIN to the transmit data output TXDOUT and clock TXCLKOUT. This mode is enabled by forcing LLBK low. Voltage Reference Output The Si5530 provides an output voltage reference that can be used by an external circuit to set the LOS threshold, slicing level, or sampling phase adjust. One possible implementation would use a resistor divider to set the control voltage for LOSLVL, SLICELVL, or PHASEADJ. A second alternative would use a DAC to set the control voltage. Using this approach, VREF would be used to establish the range of a DAC output. The reference voltage is nominally 1.25 V. Bias Generation Circuitry The SI5600 makes use of two external resistors, RXREXT and TXREXT, to set internal bias currents for the receive and transmit sections of the SI5600. The external resistors allows precise generation of bias currents that significantly reduce power consumption. The bias generation circuitry requires 3.09 k (1%) resistors connected between RXREXT/TXREXT and GND. Reference Clock The SI5600 is designed to operate with reference clock sources that are either 1/16th or 1/64th the desired transceiver data rate. The device will support operation with data rates between 9.9 Gbps and 10.7 Gbps and the reference clock should be scaled accordingly. For example, to support 10.66 Gbps operation the reference clock source would be approximately 167 MHz or 666 MHz. The REFRATE input pin is used to configure the device for operation with one of the two supported Preliminary Rev. 0.31 15 SI5600 Transmit Differential Output Circuitry The SI5600 utilizes a current-mode logic (CML) architecture to drive the high speed serial output clock and data on TXCLKOUT and TXDOUT. An example of output termination with ac coupling is shown in Figure 5. In applications where direct dc coupling is possible, the 250 nF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 5. 1.5 V VDD 50 250 nF Zo = 50 50 50 250 nF Zo = 50 50 VDD 24 mA Figure 5. CML Output Driver Termination (TXCLKOUT, TXDOUT) 16 Preliminary Rev. 0.31 SI5600 SI5600 Pinout: 195 BGA 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT [10]+ [8]- [8]+ [6]- [6]+ [4]- [4]+ [2]- [2]+ [0]- [0]+ RX CLK[1]- RX CLK[1]+ A RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT [10]- [9]- [9]+ [7]- [7]+ [5]- [5]+ [3]- [3]+ [1]- [1]+ RX CLK[2]- RX CLK[2]+ GND B RXDOUT RXDOUT [12]+ [11]+ RXCLK2 DIV RXREXT NC RXSQLCH RXCLK2 DSBL RSVD_ GND RSVD_ GND VREF SLICELVL LOSLVL GND GND C RXDOUT RXDOUT [12]- [11]- RXMSB SEL GND GND GND GND GND GND GND PHASEADJ RSVD_ GND GND RXDIN+ D RXDOUT RXDOUT [14]+ [13]+ RSVD_ GND GND VDD VDD VDD VDD VDD VDD RSVD_ VDD33 LTR GND RXDIN- E RXDOUT RXDOUT [14]- [13]- DLBK GND VDD VDD VDD VDD VDD VDD RSVD_ GND RXLOL GND GND F REF CLK+ RXDOUT [15]+ RSVD_ VDD33 GND VDD VDD VDD VDD VDD VDD RESET LOS GND TXCLKOUT+ G REF CLK- RXDOUT [15]- LLBK GND VDD VDD VDD VDD VDD VDD REFRATE VDD33 GND TXCLKOUT- H TXDIN [14]+ TXDIN [15]+ LPTM GND VDD VDD VDD VDD VDD VDD GND GND GND GND J TXDIN [14]- TXDIN [15]- TXCLK DSBL GND VDD VDD VDD VDD VDD VDD RSVD_ GND FIFOERR GND TXDOUT+ K TXDIN [12]+ TXDIN [13]+ REFSEL GND GND GND GND GND GND GND NC TXREXT GND TXDOUT- L TXDIN [12]- TXDIN [13]- TXSQLCH RSVD_ GND RSVD_ GND TXMSB SEL RSVD_ GND BWSEL FIFORST TXLOL GND GND GND GND M TXDIN [11]+ TXDIN [11]- TXDIN [9]+ TXDIN [9]- TXDIN [7]+ TXDIN [7]- TXDIN [5]+ TXDIN [5]- TXDIN [3]+ TXDIN [3]- TXDIN [1]+ TXDIN [1]- TXCLK16 TXCLK16 IN+ IN- N TXDIN [10]+ TXDIN [10]- TXDIN [8+] TXDIN [8]- TXDIN [6]+ TXDIN [6]- TXDIN [4]+ TXDIN [4]- TXDIN [2]+ TXDIN [2]- TXDIN [0]+ TXDIN [0]- TXCLK16 TXCLK16 OUT+ OUT- P Bottom View Figure 6. SI5600 Pin Configuration (Bottom View) Preliminary Rev. 0.31 17 SI5600 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A RX CLK1+ RX CLK1- RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT [10]+ [8]- [8]+ [6]- [6]+ [0]+ [0]- [2]+ [2]- [4]+ [4]- B GND RX CLK[2]+ RX CLK[2]- RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT [9]+ [9]- [10]- [7]- [7]+ [5]- [5]+ [1]+ [1]- [3]+ [3]- C GND GND LOSLVL SLICELVL VREF RSVD_ GND RSVD_ GND RXCLK2 RXSQLCH DSBL NC RXREXT RXCLK2 DIV RXDOUT RXDOUT [11]+ [12]+ D RXDIN+ GND RSVD_ GND PHASE ADJ GND GND GND GND GND GND GND RXMSB SEL RXDOUT RXDOUT [11]- [12]- E RXDIN- GND LTR RSVD_ VDD33 VDD VDD VDD VDD VDD VDD GND RSVD_ GND RXDOUT RXDOUT [13]+ [14]+ F GND GND RXLOL RSVD_ GND VDD VDD VDD VDD VDD VDD GND DLBK RXDOUT RXDOUT [13]- [14]- G TXCLKOUT+ GND LOS RESET VDD VDD VDD VDD VDD VDD GND RSVD_ VDD33 RXDOUT [15]+ REF CLK+ H TXCLKOUT- GND VDD33 REFRATE VDD VDD VDD VDD VDD VDD GND LLBK RXDOUT [15]- REF CLK- J GND GND GND GND VDD VDD VDD VDD VDD VDD GND LPTM TXDIN [15]+ TXDIN [14]+ K TXDOUT+ GND FIFOERR RSVD_ GND VDD VDD VDD VDD VDD VDD GND TXCLK DSBL TXDIN [15]- TXDIN [14]- L TXDOUT- GND TXREXT NC GND GND GND GND GND GND GND REFSEL TXDIN [13]+ TXDIN [12]+ M GND GND GND GND TXLOL FIFORST BWSEL RSVD_ GND TXMSB SEL RSVD_ GND RSVD_ GND TXSQLCH TXDIN [13]- TXDIN [12]- N TXCLK16 TXCLK16 IN- IN+ TXDIN [1]- TXDIN [1]+ TXDIN [3]- TXDIN [3]+ TXDIN [5]- TXDIN [5]+ TXDIN [7]- TXDIN [7]+ TXDIN [9]- TXDIN [9]+ TXDIN [11]- TXDIN [11]+ P TXCLK16 TXCLK16 OUT- OUT+ TXDIN [0]- TXDIN [0]+ TXDIN [2]- TXDIN [2]+ TXDIN [4]- TXDIN [4]+ TXDIN [6]- TXDIN [6]+ TXDIN [8]- TXDIN [8]+ TXDIN [10]- TXDIN [10]+ Top View Figure 7. SI5600 Pin Configuration (Transparent Top View) 18 Preliminary Rev. 0.31 SI5600 Pin Descriptions: SI5600 Pin Number(s) Name I/O Signal Level Description Bandwidth Select DSPLL. This input selects loop bandwidth of the DSPLL. BWSEL = 0: Loop bandwidth set to 12 kHz. BWSEL = 1: Loop bandwidth set to 50 kHz. Diagnostic Loopback. When this input is active low the transmit clock and data are looped back for output on RXDOUT, RXCLK1 and RXCLK2. This pin should be held high for normal operation. FIFO Error. This output is driven high when a FIFO overflow/ underflow has occurred. This output will stick high until reset by asserting FIFORST. FIFO RESET. This input when asserted high resets the read/ write FIFO pointers to their initial state. Supply Ground. M7 BWSEL I LVTTL F12 DLBK I LVTTL K3 FIFOERR O LVTTL M6 FIFORST I LVTTL B1, C1-2, D5- 11, D2, E11, E2, F11, F1-2, G11, G2, H11, H2, J11, J1-4, K2, K11, L5-11, L2, M1-4 H12 GND GND LLBK I LVTTL Line Loopback. When this input is active low the recovered clock and data are looped back for output on TXDOUT, and TXCLKOUT. This pin should be held high for normal operation. Loss-of-Signal. This output is driven low when the peak-to-peak signal amplitude is below threshold set via LOSLVL. LOS Threshold Level. Applying an analog voltage to this pin allows adjustment of the threshold used to declare LOS. Tieing this input high disables LOS detection and forces the LOS output high. G3 LOS O LVTTL C3 LOSLVL I Preliminary Rev. 0.31 19 SI5600 Pin Number(s) Name I/O Signal Level Description Loop Timed Operation. When this input is forced high, the recovered clock from the receiver is divided down and used as the reference source for the transmit CMU. The narrowband setting for the DSPLL CMU will be sufficient to provide SONET compliant jitter generation and transfer on the transmit data and clock outputs (TXDOUT,TXCLKOUT). This pin should be held low for normal operation. Lock-to-Reference This input forces a stable output clock by locking RXCLK1 and RXCLK2 to the provided reference. Driving LTR low activates this feature. No Connect. Reserved for device testing leave electrically unconnected. J12 LPTM I LVTTL E3 LTR I LVTTL C10, L4 NC D4 PHASEADJ I Sampling Phase Adjust. Applying an analog voltage to this pin allows adjustment of the sampling phase across the data eye. Tieing this input high nominally centers the sampling phase. G14, H14 REFCLK+, REFCLK- I LVPECL Differential Reference Clock. The reference clock sets the operating frequency of the PLL used to generate the high speed transmit clock. In addition, REFCLK sets the initial operating frequency used by the onboard PLL for clock and data recovery. The SI5600 will operate with reference clock frequencies that are either 1/16th or 1/64th the serial data rate (nominally 155 MHz or 622 MHz). Reference Clock Select. This input configures the SI5600 to operate with one of two reference clock frequencies. If REFRATE is held high, the device requires a reference clock that is 1/16 the serial data rate. If REFRATE is low, a reference clock at 1/64 the serial data rate is required. Reference Clock Selection. This inputs selects the reference clock source used by the CMU. When REFSEL = 0, the low speed data input clock, TXCLK16IN, is used as the CMU reference. When REFSEL = 1, the reference clock provided on REFCLK is used. H4 REFRATE I LVTTL L12 REFSEL I LVTTL 20 Preliminary Rev. 0.31 SI5600 Pin Number(s) Name I/O Signal Level Description Device Reset. Forcing this input low for a at least 1 s will cause a device reset. For normal operation, this pin should be held high. Reserved Tie to Ground. Must tie directly to GND for proper operation. Reserved Tie to VDD33. Must tie directly to VDD33 for proper operation. G4 RESET I LVTTL C6-7, D3, E12, F4, K4, M10-11, M8 E4, G12 A2-3 RSVD_GND RSVD_VDD33 RXCLK1+, RXCLK1- O LVDS Differential Clock Output 1. The clock recovered from the signal present on RXDIN is divided down by 16 and output on CLKOUT. In the absence of data, a stable clock on RXCLK1 can be maintained by asserting LTR. Differential Clock Output 2. An auxiliary output clock is provided on this pin that may be a divided down version of the high speed clock recovered from the signal present on RXDIN. The divide factor used in generating RXCLK2 is set via RXCLK2DIV. Clock Divider Select. This input selects the divide factor used to generate the RXCLK2 output. When this input is driven low, RXCLK2 is 1/16th the recovered high speed clock. When driven high, RXCLK2 is 1/64th the recovered high speed clock rate. RXCLK2 Disable. Driving this input high will disable the RXCLK2 output. This would be used to save power in applications that do not require an auxiliary clock. Differential Data Input. Clock and data are recovered from the high speed data signal present on these pins. Differential Parallel Data Output. The data recovered from the signal present on RXDIN is demultiplexed and output as a 16-bit parallel word via RXDOUT[15:0]. These outputs are updated on the rising edge of RXCLK1. Loss-of-Lock. This output is driven low when the recovered clock frequency deviates from the reference clock by the amount specified in Table 5. B2-3 RXCLK2+, RXCLK2- O LVDS C12 RXCLK2DIV I LVTTL C8 RXCLK2DSBL I LVTTL D1, E1 RXDIN+, RXDIN- RXDOUT[15:0]+, RXDOUT[15:0]- I High Speed Differential LVDS A4-14, B4-14, C13-14, D13- 14, E13-14, F13-14, G13, H13 F3 O RXLOL O LVTTL Preliminary Rev. 0.31 21 SI5600 Pin Number(s) Name I/O Signal Level Description Data Bus Receive Order. This determines the order of the received data bits on the output bus. For RXMSBSEL = 0, the first data bit received is output on RXDOUT[0] and following data bits are output on RDOUT[1] through RXDOUT[15]. For RXMSBSEL = 1, the first data bit is output on RXDOUT[15] and following data bits are output on RXDOUT[14] through RXDOUT[0]. External Bias Resistor. This resistor is used by the receiver circuitry to establish bias currents within the device. This pin must be connected to GND through a 3.09 k (1%) resistor. D12 RXMSBSEL I LVTTL C11 RXREXT C9 RXSQLCH I LVTTL Data Squelch. When this input is low the data on RXDOUT is forced to 0. Set high for normal operation. Slicing Level Adjustment. Applying an analog voltage to this pin allows adjustment of the slicing level applied to the input data eye. Tieing this input high nominally sets the slicing offset to 0. C4 SLICELVL I N1-2 TXCLK16IN+, TXCLK16IN- TXCLK16OUT+, TXCLK16OUT- I LVDS Differential Data Clock Input. The rising edge of this input clocks data present on TXDIN into the device. Divided Down Output Clock. This clock output is generated by dividing down the high speed output clock, TXCLKOUT, by a factor of 16. It is intended for use in counter clocking schemes that transfer data between the system ASIC and the SI5600. High Speed Clock Disable When this input is high, the output driver for TXCLKOUT is disabled. In applications that do not require the output data clock, the output clock driver should be disabled to save power. High Speed Clock Output. The high speed output clock, TXCLKOUT, is generated by the PLL in the clock multiplier unit. Its frequency is nominally 16 or 64 times the selected reference source. P1-2 O LVDS K12 TXCLKDSBL I LVTTL G1, H1 TXCLKOUT+, TXCLKOUT- O CML 22 Preliminary Rev. 0.31 SI5600 Pin Number(s) Name I/O Signal Level Description Differential Parallel Data Input. The 16-bit data word present on these pins is multiplexed into a high speed serial stream and output on TXDOUT. The data on these inputs is clocked into the device by the rising edge of TXCLK16IN. Differential High Speed Data Output. The 16-bit word input on TXDIN[15:0] is multiplexed into a high speed serial stream that is output on these pins. Input data is multiplexed in sequence from TXDIN0 to TXDIN15 with TXDIN0 transmitted first. This output is updated by the rising edge of TXCLKOUT. CMU Loss-of-Lock. The output is asserted low when the CMU is not phase locked to the selected reference source. Data Bus Transmit Order. For TXMSBSEL = 0, data on TXDIN[0] is transmitted first followed by TXDIN[1] through TXDIN[15]. For TXMSBSEL = 1, TXDIN[15] is transmitted first followed by TXDIN[14] through TXDIN[0]. External Bias Resistor. This resistor is used by the transmitter circuitry to establish bias currents within the device. This pin must be connected to GND through a 3.09 k (1%) resistor. J13-14, K13- 14, L13-14, M13-14, N3- 14, P3-14 TXDIN[15:0]+, TXDIN[15:0]- I LVDS K1, L1 TXDOUT+, TXDOUT- O CML M5 TXLOL O LVTTL M9 TXMSBSEL I LVTTL L3 TXREXT M12 TXSQLCH I LVTTL Transmit Data Squelch. If TXSQLCH is asserted low, the output data stream on TXDOUT will be forced to 0s. If TXSQLCH = 1, TX squelching is turned off. Supply Voltage. Nominally 1.8 V. E5-10, F5-10, G5-10, H5-10, J5-10, K5-10 VDD VDD 1.8 V Preliminary Rev. 0.31 23 SI5600 Pin Number(s) Name I/O Signal Level Description H3 VDD33 VDD33 1.8 V or 3.3 V Digital Output Supply. Must be tied to either 1.8 V or 3.3 V. When tied to 3.3 V, LVTTL compatible output voltage swings on RXLOL and LOS, TXLOL, FIFOERR are supported. Voltage Ref Voltage Reference. The SI5600 provides an output voltage reference that can be used by an external circuit to set the LOS threshold, slicing level, or sampling phase adjustment. The equivalent resistance between this pin and GND should not be less than 10 k. The reference voltage is nominally 1.25 V. C5 VREF O 24 Preliminary Rev. 0.31 SI5600 Ordering Guide Table 9. Ordering Guide Part Number Package Temperature SI5600-BC 195 BGA -40C to 85C Preliminary Rev. 0.31 25 SI5600 Package Outline Figure 8 illustrates the package details for the SI5600. Table 10 lists the values for the dimensions shown in the illustration. P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Figure 8. 195-Ball Grid Array (BGA) Table 10. Package Diagram Dimensions (mm) Symbol Min Nom Max A A1 A2 b D D1 e L S 3.50 0.65 1.35 0.65 14.90 -- -- 12.95 -- 3.65 0.70 1.45 0.70 15.00 13.00 1.00 13.00 0.50 3.80 0.75 1.55 0.75 15.10 -- -- 13.05 -- 26 Preliminary Rev. 0.31 SI5600 NOTES: Preliminary Rev. 0.31 27 SI5600 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, SiPHY, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 28 Preliminary Rev. 0.31 |
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